1. Field of the Invention
This invention relates generally to a method and structure well suited for manufacturing integrated-circuit semiconductor devices having fine geometry patterns. In particular, this invention relates to a method and structure for producing a plurality of narrow openings to surfaces of first materials, which openings are separated by narrow strips of second materials.
2. Description of the Prior Art
Techniques for producing fine geometry patterns of one material on the surface of another material are known. One of the most popular techniques, which is widely used in the semiconductor industry, involves forming a layer of photo-resist on the surface of a material, selectively exposing portions of the photoresist to ultraviolet light and developing the exposed photoresist. The size of the patterns which can be produced with this technique are limited by diffraction and reflection effects at the wavelenghts of the radiation used to expose the photoresist. Smaller patterns can be produced by analogous methods employing different photoresist materials and radiation of shorter wavelengths such as an electron beam or X-rays. A thorough discussion of the limitations of conventional photolithography can be found in the July 1975 issue of the IEEE transactions on Electron Devices.
Another technique used to produce a narrow emitter opening in a semiconductor device is disclosed in U.S. Pat. No. 3,940,288, which issued on Feb. 24, 1976 to Takagi, et al. This technique was also disclosed in a paper entitled "A New Sub-Micron Emitter Formation with Reduced Base Resistance for Ultra High-Speed Devices" by H. Kamioka, et al., presented in December 1974 to the International Electron Devices Meeting held in Washington, D.C., and published starting on page 279 in the technical digest of that meeting. This technique teaches the formation of a narrow layered sandwich (usually about 3 microns wide) of silicon nitride, silicon dioxide and silicon nitride centered over the desired location of the emitter opening on the surface of a silicon substrate. The sandwiched layer of silicon dioxide is then laterally etched inward from both sides to form with the two nitride layers a structure with an "I-beam" cross-sectional configuration. The vertical rib of remaining silicon dioxide protectively masks an underlying ribbon (approximately 0.5 micron wide) of silicon nitride while the exposed portions of silicon nitride are etched away from both sides. The overlying masking silicon dioxide rib is subsequently removed and a layer of silicon dioxide is formed on the exposed surface of the silicon substrate. The remaining ribbon of silicon nitride, which defines both the width and location of the narrow emitter opening, is then removed, thereby exposing a portion of the silicon substrate surface.
The selective lateral etching of a small-area-bounding lateral edge on an adjacent overlying layer of one material to expose a larger area of the underlying material is shown in U.S. Pat. No. 3,783,047, which issued to M. M. Paffen et al on Jan. 1, 1974, entitled "Method of Manufacturing a Semiconductor Device and Semiconductor Device Manufactured by Using Such a Method." The method taught by Paffen et al. is used to produce a semiconductor device having a small zone with one selected set of electrical properties and a larger zone with another set of electrical properties.
The use of a selective lateral etch is described by C. N. Berglund et al in a paper entitled "Undercut Isolation -- A Technique for Closely Spaced and Self-Aligned Metalization Patterns for MOS Integrated Circuits." This paper was published in September, 1973 beginning on page 1255 of Vol. 120, No. 9 of the Journal of the Electrochemical Society. C. N. Berglund et al take advantage of the shadowing effect of an undercut area etched in a two-layer insulator sandwich. Because of the masking effect of an undercut edge a thin metal film evaporated at an appropriate angle to the edge will be discontinuous at the undercut edges, resulting in electrically isolated metalization patterns at different vertical levels with negligible lateral spacing between them. Berglund et al illustrate an application for this technique by describing the design of a two-phase CCD (Charge-Coupled Device).
Although electron beam and X-ray lithographic techniques can be used to produce narrow openings separated by narrow strips of overlying materials, which make possible smaller semiconductor elements and higher chip densities than previously obtained using less advanced methods, these techniques have many disadvantages. Not only is the equipment required to practice the electron-beam technique presently very expensive, but this technique also presently requires prolonged photoresist exposure times which are unsuitable for mass production. Optimized equipment required to practice X-ray lithography on a production scale is not currently available. Moreover, in addition to the well-known hazards and fail-safe precautionary measures associated with the use of X-rays, this technique requires a high precision mask often made of heavy metal, such as gold, possessing geometries as fine as those to be produced on the surface of the material. Such masks are generally produced with electron-beam techniques and are both expensive and difficult to produce.
The size of geometries producible with the double-sided etch method of Takagi et al, or Kamioka et al, is limited by the fact that the silicon dioxide rib must be sufficiently wide to support the overhanging layer of silicon nitride. Additionally, although the lateral etch rate of silicon dioxide is in theory controllable to render the depth of undercut a function of etch time, as the depth of undercut is increased to produce an ever-narrower silicon dioxide rib, difficulty increases in controlling etch rate, etch uniformity, and hence the size of the to-be-formed geometric pattern. Further, as the etch process occurs simultaneously from two sides, the uncertainty in the size of the to-be-formed geometric pattern increases due to the combined uncertainty in the locations of the converging edges at any given time.
More recently, an improved method and structure for producing narrow openings to the surface of a first material possessing a first set of etch characteristics was disclosed in patent application Ser. No. 619,735, filed Oct. 6, 1975, by the same inventor hereof and assigned to the same assignee as this invention, which application is a continuation-in-part of co-pending application Ser. No. 581,389 filed May 27, 1975, now abandoned. The present invention, in contrast to the above-identified invention, discloses and claims a method and structure for producing a fine geometric pattern on the surface of a first material.